General goals

TOOLIP - Tools and Methods for IP


Medea+ Toolip-Mesa workshop 2003
Complex SoC Design Methodologies and Experiments
World Trade Center, room Cervin - Grenoble - November 14, 2003

MEDEA+ Applications A511 - Project

Executive Summary

TOOLIP's main goal is to address the complexity of current system design in networking, high-speed links, multimedia and automotive domains by using system-level modeling and verification techniques, applying design reuse with qualified and parametric IP cores, and providing a seamless design flow integrating existing and emerging tools.
The industrial partners and their applications will be the driving forces of TOOLIP. The close cooperation of IP users, IP providers, designers and research institutes constitutes one of the major potentials of the consortium.
TOOLIP will be crucial to the positioning of European industry, since the IP-based system-level modeling and simulation design methodology represents a breakthrough in current design methodology, which would lead to a strong impact on competitiveness and standardization. Furthermore, TOOLIP will enable the improvement of developed tools and possible future commercialization. By establishing a team with the required know-how, TOOLIP will also present new business opportunities, which would facilitate the creation of spin-off companies.

1. Project description

1.1 General goals

With the commencement of the new millennium, residential and home appliances are becoming increasingly complex systems, requiring a high level of integration. For example, in the networking area, novel services and applications (such as video on demand, home automation, teleworking, and remote health monitoring) require the transfer of multimedia and real-time data over different high-speed links (e.g. copper VDSL, wireless) using interoperable network protocols. Similarly, in the automotive industry, multimedia cars require a high level of integration of various functions in order to reduce costs.
Moreover, the great improvements in process technologies permit the integration of whole systems on a single chip. Systems-on-Chip (SoC) have favored the explosion of the information appliances market: small, mobile devices, which provide communications and information capabilities for consumer electronics, retail and industrial automation. These devices require complex electronic and high levels of system integration and need to be delivered in a very short time to the market in order to meet their market window.
In order to deal with systems of such complexity, parametric and reusable Intellectual Property (IP) cores, system level modeling and verification techniques, and a seamless design flow that integrates existing and emerging tools will be the key factors.
Recently, the application of reuse methodology for SoC has proved its validity by reducing the productivity gap and meeting critical time-to-market objectives, reducing design errors, decreasing system complexity, and easing verification and testing. In order to facilitate and spread reuse methodology in industry, a major effort is necessary in the area of IP qualification.
TOOLIP will follow a strategy of developing methodologies and tools in parallel with appropriate standardization efforts, in order to achieve the following overall objectives:

  • Shorten design time cycles
  • First time silicon success
  • Reducing design complexity
  • Ease simulation, verification and test
  • Make "reuse" a feasible reality

The industrial partners and their applications will be the driving forces in TOOLIP. The close co-operation of IP users, IP providers, EDA companies and designers will guarantee market-oriented solutions and enforce synergetic effects. The TOOLIP consortium is completed by institutes and universities with long-term and relevant experience in the mentioned application areas and in co-operation with industrial partners. In particular, some industrial partners of TOOLIP will demonstrate the feasibility of the methods and tools developed in TOOLIP by applying the results in demonstrators realized also in the project. Furthermore, TOOLIP will support IP creation and its integration in SoC that will be the basis of new advanced products.
The first aim of the consortium will be to offer a specification of reuse-oriented requirements for supporting the exchange of qualified IP, including general constraints and guidelines, as well as executable specifications for intra- and inter-company exchange.
Furthermore, qualified IP will be made accessible via methodologies and tools, which will focus on the efficient implementation of all relevant IP management functions, including creation, storage, intelligent analysis and retrieval, validation and simulation. This effort will lead to a standardized IP platform development, which will enable IP inter-company exchange and thus the integration of third party IP.

Figure 1: TOOLIP Design Flow

The TOOLIP design flow will also consider methods and tools for supporting IP checks done by IP vendors (called IP compliance checks), or customizable to the IP user needs (called IP entrance checks). All checks will be supported using validation and distributed simulation techniques which will focus on solving existing interoperability and large-scale performance evaluation problems. Finally, TOOLIP considers flexible parameterization formats for supporting application-specific customization by the IP provider, or design adaptation by the IP user.
Several demonstration platforms are planned which will focus on relevant developments defined by the industrial partners, involving system integration of large and complex designs, in particular ones dealing with SoC issues.
Besides the definition of efficient and innovative methods and tools, a second important aim of TOOLIP involves monitoring and active participation in defining and influencing international standards which support inter-company IP reuse. Active contribution of European industry will directly influence the success of products and tools in the market. Furthermore, the interaction between large European companies within a common project will accelerate this necessary process before IP exchange can be realized beyond the borders of intra-company reuse.
Thus, within TOOLIP, it is planned to promote important contributions to standardization. We hope that TOOLIP will trigger active participation in various relevant standardization activities, involving:

a) the Virtual Socket Interface Alliance (VSIA) for characterization of all relevant issues for reuse of components and their interfaces.
b) distributed simulation (IEEE Standard HLA - High Level Architecture; a prototype is currently being developed by the US Department of Defense - DMSO 1997),
c) specification, design, and testing of a system-level design language supporting interoperability of tools and languages within an existing design flow in order to realize long-term reuse opportunities (Open standard: OSCI - Open SystemC Initiative, or OMG's CCM - CORBA Component Model),
d) new SoC design methodologies for eventual adoption as de-facto standard, and
e) standardization and integration of an IP platform-based library which may involve intellectual property arising from internal sources or acquired from external sources; this could involve flexible parameterization formats, state of the art data storage and data retrieval techniques, multiple levels of abstraction, and a comprehensive design and interface style based on an open, widely accepted standard language.

1.2 Strategic relevance (relevance for MEDEA+)

This project proposal is fully in line with work area 2.1 of the MEDEA+ program, "System on Chip requirements in design methodologies and tools".
In order that European industry can obtain and safeguard a leadership position in the driving forces of Internet, digital consumer electronics, and wireless communications (cf. MEDEA White Book, Vers. 1.0, pp. 19) it is essential that large scale devices are designed in a time predictable manner, with high system reliability, and reduced overall system cost. Within the above context, TOOLIP's major contribution is to create a seamless environment for supporting IP reuse via a rich, standardized IP platform which

  • implements multiple levels of abstraction,
  • enables hardware/software co-design, and
  • integrates and provides interoperability between several state of the art tools involving IP management, IP check, IP selection, IP modification, IP validation, and IP simulation functions.

The adoption of best practices focusing on IP reuse for large scale system design would increase competitiveness of the European industry in designing complex electronic systems. Without TOOLIP's innovative methods and tools, the preservation of small and medium information technology enterprises will be stifled by the associated system development risks, since modern hi-tech products have a very short life span, and missing the "marketing window" for new products is usually very costly.
Furthermore, the close relationship between microelectronic companies and system houses will support TOOLIP's effort in the direction of reusing IP from key domains, such as broadband communications, multimedia, processor cores, and small offices and home offices (SOHO), and driving standardization processes with respect to Europe's needs.

© Andreas Vörg, FZI Karlsruhe, 2001-03